1. Field of the Invention
This invention relates to techniques for increasing rated voltage of field-effect semiconductor devices.
2. Description of the Prior Art
In the case of field-effect semiconductor devices, both a source region and a body region are formed adjacent to each other at one surface of a semiconductor substrate thereof, and a drift region is accordingly formed at the other surface of the substrate. In this specification, the surface where both the source region and the body region are formed will be defined as a top surface, and the other surface where the drift region is formed will be defined as a bottom surface.
In the case of controlling a large quantity of electric power by this semiconductor device, a plurality of units are formed at the top surface of the semiconductor substrate where each unit is defined by a structure formed by one source region and one body region adjacent to each other. FIG. 13 shows an example in the case that the plurality of source regions S and the plurality of body regions G are arranged alternately and in parallel with each other at the top surface of the substrate ST.
In the case of such a semiconductor device, it is necessary to connect externally the source regions S. For this reason, a single source pad is required for connecting a lead wire from outside to the semiconductor device. The single source pad is connected to all of the source regions S. It is necessary to lessen each distance between the source pad and each source region S so as to lower the resistance between the source and the drain in the semiconductor device. It is also necessary for the source pad to have a certain spreading thereof so as to connect it to the lead wire. For these reasons, the source pad is formed in an area for covering the overall source regions S. In FIG. 14, SP shows an example of the source pad.
There is a necessity of gate electrodes for facing each body region G. An insulation film is needed between the gate electrodes and the body regions. An example of the gate electrodes is illustrated by GE in FIG. 14. It is necessary for these gate electrodes GE to be insulated from the source pad SP and to be connected externally. For this reason, the gate pad is necessary. As described above, the source pad SP covers an area Z (which will be designated as an element area thereafter) where the source regions S and the drain regions G are arranged adjacent to each other. After all, there is no way but the gate pad GP is provided in other areas than the element area Z. FIG. 14 illustrates an example of the gate pad GP provided in other areas than the element area Z. A gate wiring GS is used for connecting the gate pad GP to the gate electrodes GE. It is also preferable that the resistance between the gate pad GP and the gate wiring GE is low. In the case of FIG. 14, the resistance between the gate pad GP and the gate wiring GS is reduced by contacting the gate pad GP with the gate wiring GS over a broad range of areas thereof. FIG. 10 shows a cross-sectional view taken substantially along line X--X of FIG. 14. Both of these drawings are not, however, consistent with each other since FIG. 14 is just a sort of model. As shown in FIG. 10, the source region S and the body regions G1 and G2 are formed at the top surface STa of the substrate ST. The drain region D is formed at the bottom surface STb of the substrate ST. The source region S, the drain region D and the substrate ST have the same conductivity type, and the body regions G1 and G2 have opposite conductivity type. The source pad SP is formed on a top surface of the source region S, and the source pad SP and the source region S are connected directly. An insulation film 300 is formed to cover the top surface STa at the area other than the element area Z, and the gate wiring GS is formed on a top surface 300a of the insulation film 300. The insulation film 300 is not formed above the body region G1, and the gate electrode GE is connected to the gate wiring GS. The gate electrode GE faces the body region G1 but is insulated from the body region G1 by an insulation film 304. The gate pad GP is formed on a top surface of the gate wiring GS. The source pad SP and the gate electrode GE are insulated by an insulation layer 302. A drain electrode DE is formed on the bottom surface STb of the substrate ST.
According to this structure, the gate pad GP contacts with the gate wiring GS over a broad range of areas in the area other than the element area Z to reduce the resistance between the gate pad GP and the gate electrode GE.
In the case of such a structure, high voltages are, however, often applied to the field insulation film 300 under the gate pad GP when the semiconductor device is off. Accordingly, the field insulation film 300 has to be sufficiently increased in thickness so as to secure a high rated voltage. There is, however, the disadvantage in that the characteristics of the field-effect semiconductor device become unstable by the influence of the resulting stress in the insulating film 300 in the case of increasing the thickness of the insulation film 300. In addition, there is the disadvantage that the thick insulation film 300 is formed in the area other than the element area Z and the thin insulation film 304 is formed in the element area Z. This makes the production process complicated.
Japanese Laid-Open Patent Publication No. 60-262468 discloses a technique for securing high rated voltage without increasing the thickness of the field insulation film. FIG. 11 shows the technique disclosed in the Japanese publication. Parts that are the same as those in FIG. 10 are given like reference symbols and their description will not be repeated. As shown in FIG. 11, in a MOS field-effect transistor having a double diffused structure, this technique forms an electrically floating diffusion region 402 of the same conductivity type with that of the body region G at the top surface of the substrate between the body regions G spaced from each other. This diffusion region 402 is formed in the form of a surface widening over almost all regions of the area formed between the plurality of body regions G.
In the case that the diffusion layer 402 of the opposite conductivity type to that of the semiconductor substrate is formed at the top surface of the semiconductor substrate, a depletion layer 404 spreading on the side of the semiconductor substrate from the diffusion layer 402 is formed when a high voltage is applied to the drain region D. This depletion layer 404 connects to a depletion layer 408 from the body region G, and alleviates an electric field at the semiconductor substrate top surface to secure high rated voltage.
However, when the above-mentioned diffusion region 402 is formed in the form of the surface widening so as to range over almost all the regions of the area formed between the plurality of body regions G, the gate wiring GS cannot be formed above the diffusion region 402 in order to maintain the diffusion region 402 in the electrically floating state, resulting in reducing the contact area between the gate pad and the gate wiring.
As shown in FIG. 12, for forming an insulation film 502 having no contact holes to an electrically floating diffusion region 500 and having contact holes 506 to the other region G, for example, a photolithography process is also required for individually preparing the contact holes 506 apart from the photolithography process required for forming the region G and the region 500.